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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:53:42 01/29/2008 
-- Design Name: 
-- Module Name:    Mem_Signal_mux - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mem_signal_mux is
    Port ( A_M : in  STD_LOGIC_VECTOR (0 to 22);
           A_F : in  STD_LOGIC_VECTOR (0 to 22);
           DQ_M_I : out  STD_LOGIC_VECTOR (0 to 15);
           DQ_M_O : in  STD_LOGIC_VECTOR (0 to 15);
           DQ_M_T : in  STD_LOGIC_VECTOR (0 to 15);
           DQ_F_I : out  STD_LOGIC_VECTOR (0 to 15);
           DQ_F_O : in  STD_LOGIC_VECTOR (0 to 15);
           DQ_F_T : in  STD_LOGIC_VECTOR (0 to 15);
           OEN_M : in  STD_LOGIC;
           OEN_F : in  STD_LOGIC;
           WEN_M : in STD_LOGIC;
           WEN_F : in STD_LOGIC;
           WEN : out STD_LOGIC;
           CEN_M : in  STD_LOGIC;
           CEN_F : in  STD_LOGIC;
           A_Out : out  STD_LOGIC_VECTOR (0 to 22);
           DQ_I : in  STD_LOGIC_VECTOR (0 to 15);
           DQ_O : out  STD_LOGIC_VECTOR (0 to 15);
           DQ_T : out  STD_LOGIC_VECTOR(0 to 15);
           CEN_M_O : out  STD_LOGIC;
           CEN_F_O : out  STD_LOGIC;
           OEN : out  STD_LOGIC);
end mem_signal_mux;

architecture Behavioral of mem_signal_mux is

begin


CEN_M_O<=CEN_M;

CEN_F_O<=CEN_F;

OEN<='0' when (OEN_M ='0' or OEN_F='0') else '1';


process(DQ_M_T, DQ_F_T)
variable i: integer range 0 to 15 :=0;
begin
   for i in 0 to 15 loop
      if (DQ_M_T(i) ='0' or DQ_F_T(i) ='0') then
            DQ_T(i)<='0';
      else
            DQ_T(i)<='1';
      end if;
   end loop;
end process;

A_Out<=A_F when CEN_F='0' else A_M;

DQ_O<=DQ_F_O when CEN_F='0' else DQ_M_O;

WEN<=WEN_F when CEN_F='0' else WEN_M;

DQ_M_I<=DQ_I;

DQ_F_I<=DQ_I;




end Behavioral;

